Central processing unit (CPU) may incur unexpected errors during computation. For example, space radiation may cause a register bit to randomly flip, thus causing computational errors. This type of random errors is not permissible in mission critical operations. Current methods use either temporal redundancy or spatial redundancy to increase the reliability of computational units such as arithmetic logic units (ALUs). Temporal redundancy means to use the same circuit multiple times to repeatedly perform the same operations. The results of these repeated operations may be compared to determine if there is a discrepancy. A discrepancy means that there is an error in the computation. Spatial redundancy means to use multiple copies of the same circuit to perform a same operation and thus compare the results from these circuits to determine if there is discrepancy among the results. Similarly, a discrepancy means that there is an error in the computation.
Temporal redundancy has the advantage of requiring less circuit area (only need one ALU), but has the disadvantage of taking twice as long (and twice execution power consumption) to complete one computation. In contrast, spatial redundancy has the advantage of achieving unity performance, but has the disadvantage of occupying twice circuit area and again twice the execution power consumption. Both temporal and spatial redundancies require only minimal increase in design complexity. Other methods to increase reliability may include residual computation which attempts to minimize the area and power consumption while maintaining unity performance. Unfortunately, the residual computation method significantly increases the design complexity.